Integrated circuit design involves the creation of electronic components, such as transistors, resistors, capacitors and the metallic interconnect of these components onto a piece of a semiconductor, such as silicon. A typical standard cell based integrated circuit design cycle involves multiple stages such as system specification, architectural design, functional/logic design, static timing analysis, physical design, timing optimization, and fabrication.
Traditional static timing analysis and timing optimization uses pre-characterized cell delay data of a standard cell library to verify timing of an integrated circuit design. Prior to the integrated circuit design, exhaustive SPICE (Simulation Program with Integrated Circuit Emphasis) simulations are performed for each standard cell based upon a matrix of various input data slew rates and output loads that mimic conditions that the cell may encounter during operation.
For standard cell technologies with transistor gate lengths greater than 1 um (micrometer), the overall circuit timing behavior is generally dominated by the delay through the standard cells. As such, traditional static timing analysis generally predicts an integrated circuit design's timing characteristics with acceptable accuracy. However, for technologies that have gate lengths less than 0.1 um, timing delays through interconnecting wires may be comparable to, or greater than, timing delays through the standard cells. Therefore, traditional static timing analysis for these technologies may result in inaccurate timing simulations or overly conservative timing optimizations.